On Fri 08 Jul 23:59 PDT 2022, Manivannan Sadhasivam wrote:
> On Thu, Jul 07, 2022 at 09:08:58AM -0700, Bjorn Andersson wrote:
> > The timer node needs ranges specified to map the 1-cell children to the
> > 2-cell address range used in /soc. This addition never made it into the
> > patch that was posted and merged, so add it now.
> >
> > Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 2bdb42c88311..37a4cd6f85b6 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -1667,6 +1667,7 @@ timer@17c20000 {
> > reg = <0x0 0x17c20000 0x0 0x1000>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > + ranges = <0 0 0 0x20000000>;
>
> Even though this looks correct, I'm wondering why other SoCs are defining the
> child addresses in 2 cells. I don't think the timer frames can go beyond 32bit
> address space. Should we fix them too?
>
Neither addresses nor sizes used for mmio need more than 32 bits, but
ranges and dma-ranges are expressed in #size-cells. So unless these
cells are 2 there's no way for us to express the fact that (most of) our
busses uses 36 address bits.
And we need to be able to do this, because the SMMU on multiple
platforms claims that the bus is 40 address bits, so we end up running
into issues with the upper 4 bits of IOVAs being truncated.
Regards,
Bjorn
> But for this patch,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
>
> Thanks,
> Mani
>
> >
> > frame@17c21000 {
> > frame-number = <0>;
> > --
> > 2.35.1
> >
>
> --
> ??????????????????????????? ????????????????????????
