Hi,
On Mon, Jul 11, 2022 at 1:26 AM Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
> registers is cqhci, not core.
>
> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>
> ---
>
> Not tested on hardware, but no practical impact is expected, because
> supports-cqe is not defined.
Maybe the schema should enforce this? If "cqhci" is in reg-names then
you must have supports-cqe and vice versa?
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 77bff81af433..7664ef7e4da9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
> sdhc_1: mmc@4744000 {
> compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
> - reg-names = "hc", "core";
> + reg-names = "hc", "cqhci";
Another possible fix would be to just delete the second register
range. Then it could be added back in once "supports-cqe" was added.
-Doug
