On 07/07/2022 11:06, Johan Hovold wrote:
On Mon, Jul 04, 2022 at 06:27:45PM +0300, Dmitry Baryshkov wrote:
On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++--
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index c40ba753707c..ee5414522e3c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
[...]
@@ -623,6 +624,50 @@ allOf:
- resets
- reset-names
+ # On newer chipsets support either 1 or 8 msi interrupts
+ # On older chipsets it's always 1 msi interrupt
+ - if:
+ properties:
+ compatibles:
This still has the misspelled property name here (plural s) so the
conditional is always false.
I know I included a fix for this in my follow-on series, but if you are
respinning the series anyway you should fix it up.
Done, thanks a lot pointing me to it.
+ contains:
+ enum:
+ - qcom,pcie-msm8996
[...]
--
With best wishes
Dmitry
