On Wed, Jul 06, 2022 at 03:04:44PM +0200, Konrad Dybcio wrote: > > > On 5.07.2022 15:39, Christian Marangi wrote: > > Enable usb phy by default. When the usb phy were pushed, half of them > > were flagged as disabled by mistake. Fix this to correctly init dwc3 > > node on any ipq8064 based SoC. > Are you sure they are used on *all* devices? If not, you will > lose power by enabling unused hw.. > > Konrad Well there could be device that have no usb at all... so honestly enabling one of them is also wrong. Should I disable the other and enable it for the upstream device? Also it's all handled by dummy vbus so i think we can ignore the losing power thing. (this thing is old) > > > > Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx> > > Tested-by: Jonathan McDowell <noodles@xxxxxxxx> > > --- > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ---- > > 1 file changed, 4 deletions(-) > > > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > index b2faa4a067e9..9c32c637ea46 100644 > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > @@ -1177,8 +1177,6 @@ hs_phy_0: phy@100f8800 { > > clocks = <&gcc USB30_0_UTMI_CLK>; > > clock-names = "ref"; > > #phy-cells = <0>; > > - > > - status = "disabled"; > > }; > > > > ss_phy_0: phy@100f8830 { > > @@ -1187,8 +1185,6 @@ ss_phy_0: phy@100f8830 { > > clocks = <&gcc USB30_0_MASTER_CLK>; > > clock-names = "ref"; > > #phy-cells = <0>; > > - > > - status = "disabled"; > > }; > > > > usb3_0: usb3@100f8800 { -- Ansuel