On 05/07/2022 15:39, Christian Marangi wrote:
> Add speedbin efuse nvmem binding needed for the opp table for the CPU
> freqs.
>
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> Tested-by: Jonathan McDowell <noodles@xxxxxxxx>
> ---
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 777851bed95a..45e713387deb 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -862,6 +862,9 @@ tsens_calib: calib@400 {
> tsens_calib_backup: calib_backup@410 {
> reg = <0x410 0xb>;
> };
> + speedbin_efuse: speedbin@c0 {
Wrong order of nodes. 0xc0 is before 0x410.
Best regards,
Krzysztof
