Only some USB and combo PHYs have a second dp_com control block.
Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
index d1d4a468acc3..7cdc1cce06cf 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
@@ -31,10 +31,8 @@ properties:
- qcom,sm8450-qmp-gen4x2-pcie-phy
reg:
- minItems: 1
items:
- description: Address and length of PHY's common serdes block.
- - description: Address and length of PHY's DP_COM control block.
"#address-cells":
enum: [ 1, 2 ]
--
2.35.1
