On Tue, 28 Jun 2022 10:57:07 +0200, Johan Hovold wrote:
> Use the new phy-mux clock implementation for the PCIe pipe clock muxes
> so that the pipe clock source is set to the QMP PHY PLL when the
> downstream pipe clock is enabled and restored to the always-on XO when
> it is again disabled.
>
> This is needed to prevent the corresponding GDSC from hanging when
> enabling or disabling the PCIe power domain, something which requires a
> ticking source.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe
commit: 9410fb940114444f37a0b787bd84077b61d76bf6
Best regards,
--
Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
