On Tue, 21 Jun 2022 at 19:07, Yassine Oudjana <yassine.oudjana@xxxxxxxxx> wrote:
>
> From: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx>
>
> Replace parent_names in PLLs, secondary muxes and primary muxes with
> parent_data. For primary muxes there were never any *cl_pll_acd clocks,
> so instead of adding them, put the primary PLLs in both PLL_INDEX and
> ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when
> setting parent since we always want ACD when using the primary PLLs.
>
> Signed-off-by: Yassine Oudjana <y.oudjana@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/clk-cpu-8996.c | 79 ++++++++++++++++++++-------------
> 1 file changed, 47 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
> index b3ad9245874d..cdb7b2ef3367 100644
> --- a/drivers/clk/qcom/clk-cpu-8996.c
> +++ b/drivers/clk/qcom/clk-cpu-8996.c
> @@ -112,14 +112,18 @@ static const struct alpha_pll_config hfpll_config = {
> .early_output_mask = BIT(3),
> };
>
> +static const struct clk_parent_data pll_parent[] = {
> + { .fw_name = "xo" },
> +};
> +
> static struct clk_alpha_pll pwrcl_pll = {
> .offset = PWRCL_REG_OFFSET,
> .regs = prim_pll_regs,
> .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pwrcl_pll",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> + .parent_data = pll_parent,
> + .num_parents = ARRAY_SIZE(pll_parent),
> .ops = &clk_alpha_pll_huayra_ops,
> },
> };
> @@ -130,8 +134,8 @@ static struct clk_alpha_pll perfcl_pll = {
> .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> .clkr.hw.init = &(struct clk_init_data){
> .name = "perfcl_pll",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> + .parent_data = pll_parent,
> + .num_parents = ARRAY_SIZE(pll_parent),
> .ops = &clk_alpha_pll_huayra_ops,
> },
> };
> @@ -190,8 +194,8 @@ static struct clk_alpha_pll pwrcl_alt_pll = {
> .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "pwrcl_alt_pll",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> + .parent_data = pll_parent,
> + .num_parents = ARRAY_SIZE(pll_parent),
> .ops = &clk_alpha_pll_hwfsm_ops,
> },
> };
> @@ -204,8 +208,8 @@ static struct clk_alpha_pll perfcl_alt_pll = {
> .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "perfcl_alt_pll",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> + .parent_data = pll_parent,
> + .num_parents = ARRAY_SIZE(pll_parent),
> .ops = &clk_alpha_pll_hwfsm_ops,
> },
> };
> @@ -252,6 +256,9 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index)
> u32 val;
>
> val = index;
> + /* We always want ACD when using the primary PLL */
> + if (val == PLL_INDEX)
> + val = ACD_INDEX;
> val <<= cpuclk->shift;
>
> return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
> @@ -282,17 +289,24 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = {
> .determine_rate = clk_cpu_8996_pmux_determine_rate,
> };
>
> +static const struct clk_parent_data pwrcl_smux_parents[] = {
> + { .fw_name = "xo" },
> + { .hw = &pwrcl_pll_postdiv.hw },
> +};
> +
> +static const struct clk_parent_data perfcl_smux_parents[] = {
> + { .fw_name = "xo" },
> + { .hw = &perfcl_pll_postdiv.hw },
> +};
> +
> static struct clk_regmap_mux pwrcl_smux = {
> .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
> .shift = 2,
> .width = 2,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "pwrcl_smux",
> - .parent_names = (const char *[]){
> - "xo",
> - "pwrcl_pll_postdiv",
> - },
> - .num_parents = 2,
> + .parent_data = pwrcl_smux_parents,
> + .num_parents = ARRAY_SIZE(pwrcl_smux_parents),
> .ops = &clk_regmap_mux_closest_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -304,16 +318,27 @@ static struct clk_regmap_mux perfcl_smux = {
> .width = 2,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "perfcl_smux",
> - .parent_names = (const char *[]){
> - "xo",
> - "perfcl_pll_postdiv",
> - },
> - .num_parents = 2,
> + .parent_data = perfcl_smux_parents,
> + .num_parents = ARRAY_SIZE(perfcl_smux_parents),
> .ops = &clk_regmap_mux_closest_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> };
>
> +static const struct clk_parent_data pwrcl_pmux_parents[] = {
> + [SMUX_INDEX] = { .hw = &pwrcl_smux.clkr.hw },
> + [PLL_INDEX] = { .hw = &pwrcl_pll.clkr.hw },
> + [ACD_INDEX] = { .hw = &pwrcl_pll.clkr.hw },
> + [ALT_INDEX] = { .hw = &pwrcl_alt_pll.clkr.hw },
> +};
> +
> +static const struct clk_parent_data perfcl_pmux_parents[] = {
> + [SMUX_INDEX] = { .hw = &perfcl_smux.clkr.hw },
> + [PLL_INDEX] = { .hw = &perfcl_pll.clkr.hw },
> + [ACD_INDEX] = { .hw = &perfcl_pll.clkr.hw },
> + [ALT_INDEX] = { .hw = &perfcl_alt_pll.clkr.hw },
> +};
> +
> static struct clk_cpu_8996_pmux pwrcl_pmux = {
> .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
> .shift = 0,
> @@ -323,13 +348,8 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = {
> .nb.notifier_call = cpu_clk_notifier_cb,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "pwrcl_pmux",
> - .parent_names = (const char *[]){
> - "pwrcl_smux",
> - "pwrcl_pll",
> - "pwrcl_pll_acd",
> - "pwrcl_alt_pll",
> - },
> - .num_parents = 4,
> + .parent_data = pwrcl_pmux_parents,
Please use parent_hws here and below.
> + .num_parents = ARRAY_SIZE(pwrcl_pmux_parents),
> .ops = &clk_cpu_8996_pmux_ops,
> /* CPU clock is critical and should never be gated */
> .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> @@ -345,13 +365,8 @@ static struct clk_cpu_8996_pmux perfcl_pmux = {
> .nb.notifier_call = cpu_clk_notifier_cb,
> .clkr.hw.init = &(struct clk_init_data) {
> .name = "perfcl_pmux",
> - .parent_names = (const char *[]){
> - "perfcl_smux",
> - "perfcl_pll",
> - "perfcl_pll_acd",
> - "perfcl_alt_pll",
> - },
> - .num_parents = 4,
> + .parent_data = perfcl_pmux_parents,
> + .num_parents = ARRAY_SIZE(perfcl_pmux_parents),
> .ops = &clk_cpu_8996_pmux_ops,
> /* CPU clock is critical and should never be gated */
> .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> --
> 2.36.1
>
--
With best wishes
Dmitry
