On Tue, Jun 21, 2022 at 11:54:54AM +0300, Baruch Siach wrote: > From: Selvam Sathappan Periakaruppan <quic_speriaka@xxxxxxxxxxx> > > IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that > platform. > > The code is based on downstream[1] Codeaurora kernel v5.4 (branch > win.linuxopenwrt.2.0). > > Split out the DBI registers access part from .init into .post_init. DBI > registers are only accessible after phy_power_on(). > > [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Acked-by: Stanimir Varbanov <svarbanov@xxxxxxxxxx> > Tested-by: Robert Marko <robert.marko@xxxxxxxxxx> > Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@xxxxxxxxxxx> > Signed-off-by: Baruch Siach <baruch.siach@xxxxxxxxx> Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx> Johan
