[PATCH] clk: qcom: clk-cpu-8996: use parent_hws/_data instead of parent_names

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Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

The ACD clocks (which were not defined before) are modelled using 1:1
fixed factor clocks to fill the gap in CPU clocks definitions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
 drivers/clk/qcom/clk-cpu-8996.c | 139 ++++++++++++++++++++++----------
 1 file changed, 98 insertions(+), 41 deletions(-)

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 4a4fde8dd12d..03abca379d47 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -117,7 +117,9 @@ static struct clk_alpha_pll perfcl_pll = {
 	.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "perfcl_pll",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_huayra_ops,
 	},
@@ -129,7 +131,9 @@ static struct clk_alpha_pll pwrcl_pll = {
 	.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pwrcl_pll",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_huayra_ops,
 	},
@@ -161,7 +165,9 @@ static struct clk_alpha_pll perfcl_alt_pll = {
 	.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "perfcl_alt_pll",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_hwfsm_ops,
 	},
@@ -175,12 +181,70 @@ static struct clk_alpha_pll pwrcl_alt_pll = {
 	.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "pwrcl_alt_pll",
-		.parent_names = (const char *[]){ "xo" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "xo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_hwfsm_ops,
 	},
 };
 
+static struct clk_fixed_factor perfcl_pll_main = {
+	.hw.init = &(struct clk_init_data) {
+		.name = "perfcl_pll_main",
+		.parent_hws = (const struct clk_hw*[]){
+			&perfcl_pll.clkr.hw,
+		},
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+	.mult = 1,
+	.div = 2,
+};
+
+static struct clk_fixed_factor pwrcl_pll_main = {
+	.hw.init = &(struct clk_init_data) {
+		.name = "pwrcl_pll_main",
+		.parent_hws = (const struct clk_hw*[]){
+			&pwrcl_pll.clkr.hw,
+		},
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+	.mult = 1,
+	.div = 2,
+};
+
+static struct clk_fixed_factor perfcl_pll_acd = {
+	.hw.init = &(struct clk_init_data) {
+		.name = "perfcl_pll_acd",
+		.parent_hws = (const struct clk_hw*[]){
+			&perfcl_pll.clkr.hw,
+		},
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+	.mult = 1,
+	.div = 1,
+};
+
+static struct clk_fixed_factor pwrcl_pll_acd = {
+	.hw.init = &(struct clk_init_data) {
+		.name = "pwrcl_pll_acd",
+		.parent_hws = (const struct clk_hw*[]){
+			&pwrcl_pll.clkr.hw,
+		},
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+	.mult = 1,
+	.div = 1,
+};
+
 struct clk_cpu_8996_mux {
 	u32	reg;
 	u8	shift;
@@ -257,11 +321,12 @@ static struct clk_cpu_8996_mux pwrcl_smux = {
 	.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
 	.shift = 2,
 	.width = 2,
+	.pll = &pwrcl_pll_main.hw,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "pwrcl_smux",
-		.parent_names = (const char *[]){
-			"xo",
-			"pwrcl_pll_main",
+		.parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+			{ .hw = &pwrcl_pll_main.hw },
 		},
 		.num_parents = 2,
 		.ops = &clk_cpu_8996_mux_ops,
@@ -273,11 +338,12 @@ static struct clk_cpu_8996_mux perfcl_smux = {
 	.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
 	.shift = 2,
 	.width = 2,
+	.pll = &perfcl_pll_main.hw,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "perfcl_smux",
-		.parent_names = (const char *[]){
-			"xo",
-			"perfcl_pll_main",
+		.parent_data = (const struct clk_parent_data[]){
+			{ .fw_name = "xo", .name = "xo_board" },
+			{ .hw = &perfcl_pll_main.hw },
 		},
 		.num_parents = 2,
 		.ops = &clk_cpu_8996_mux_ops,
@@ -294,11 +360,11 @@ static struct clk_cpu_8996_mux pwrcl_pmux = {
 	.nb.notifier_call = cpu_clk_notifier_cb,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "pwrcl_pmux",
-		.parent_names = (const char *[]){
-			"pwrcl_smux",
-			"pwrcl_pll",
-			"pwrcl_pll_acd",
-			"pwrcl_alt_pll",
+		.parent_hws = (const struct clk_hw*[]){
+			&pwrcl_smux.clkr.hw,
+			&pwrcl_pll.clkr.hw,
+			&pwrcl_pll_acd.hw,
+			&pwrcl_alt_pll.clkr.hw,
 		},
 		.num_parents = 4,
 		.ops = &clk_cpu_8996_mux_ops,
@@ -316,11 +382,11 @@ static struct clk_cpu_8996_mux perfcl_pmux = {
 	.nb.notifier_call = cpu_clk_notifier_cb,
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "perfcl_pmux",
-		.parent_names = (const char *[]){
-			"perfcl_smux",
-			"perfcl_pll",
-			"perfcl_pll_acd",
-			"perfcl_alt_pll",
+		.parent_hws = (const struct clk_hw*[]){
+			&perfcl_smux.clkr.hw,
+			&perfcl_pll.clkr.hw,
+			&perfcl_pll_acd.hw,
+			&perfcl_alt_pll.clkr.hw,
 		},
 		.num_parents = 4,
 		.ops = &clk_cpu_8996_mux_ops,
@@ -338,6 +404,13 @@ static const struct regmap_config cpu_msm8996_regmap_config = {
 	.val_format_endian	= REGMAP_ENDIAN_LITTLE,
 };
 
+static struct clk_hw *cpu_msm8996_clks_hw[] = {
+	&perfcl_pll_main.hw,
+	&pwrcl_pll_main.hw,
+	&perfcl_pll_acd.hw,
+	&pwrcl_pll_acd.hw,
+};
+
 static struct clk_regmap *cpu_msm8996_clks[] = {
 	&perfcl_pll.clkr,
 	&pwrcl_pll.clkr,
@@ -354,32 +427,16 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
 {
 	int i, ret;
 
-	perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
-						       "perfcl_pll",
-						       CLK_SET_RATE_PARENT,
-						       1, 2);
-	if (IS_ERR(perfcl_smux.pll)) {
-		dev_err(dev, "Failed to initialize perfcl_pll_main\n");
-		return PTR_ERR(perfcl_smux.pll);
-	}
-
-	pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
-						      "pwrcl_pll",
-						      CLK_SET_RATE_PARENT,
-						      1, 2);
-	if (IS_ERR(pwrcl_smux.pll)) {
-		dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
-		clk_hw_unregister(perfcl_smux.pll);
-		return PTR_ERR(pwrcl_smux.pll);
+	for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks_hw); i++) {
+		ret = devm_clk_hw_register(dev, cpu_msm8996_clks_hw[i]);
+		if (ret)
+			return ret;
 	}
 
 	for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
 		ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
-		if (ret) {
-			clk_hw_unregister(perfcl_smux.pll);
-			clk_hw_unregister(pwrcl_smux.pll);
+		if (ret)
 			return ret;
-		}
 	}
 
 	clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
-- 
2.35.1




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