On Sun, Jun 12, 2022 at 01:18:35PM +0300, Baruch Siach wrote: > From: Selvam Sathappan Periakaruppan <quic_speriaka@xxxxxxxxxxx> > > IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that > platform. > > The code is based on downstream[1] Codeaurora kernel v5.4 (branch > win.linuxopenwrt.2.0). > > Split out the DBI registers access part from .init into .post_init. DBI > registers are only accessible after phy_power_on(). > > [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ > > Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@xxxxxxxxxxxxxx> > Signed-off-by: Baruch Siach <baruch.siach@xxxxxxxxx> > --- > v7: > > * Rebase on v5.19-rc1 (Bjorn Helgaas) > > v6: > > Address Bjorn Helgaas comments: > > * Rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL > > * Drop a vague comment about ASPM configuration > > * Add a comment about the source of delay periods > > v5: > > * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) > > v4: > > * Rebase on v5.16-rc1 > > v3: > * Drop speed setup; rely on generic code (Rob Herring) > > * Drop unused CLK_RATE macros (Bjorn Helgaas) > > * Minor formatting fixes (Bjorn Helgaas) > > * Add reference to downstream Codeaurora kernel tree (Bjorn Helgaas) > > v2: > * Drop ATU configuration; rely on common code instead > > * Use more common register macros > > * Use bulk clk and reset APIs > --- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > drivers/pci/controller/dwc/pcie-qcom.c | 140 +++++++++++++++++++ > 2 files changed, 141 insertions(+) Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
