Add missing registers, verified against: - msm-4.4's phy-qcom-ufs-qmp-v3.h Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> --- .../qualcomm/phy-qcom-qmp-qserdes-com-v3.h | 25 +++++++++++++++++++ .../qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h index a61f8d36d01e..c0bd54e0e7b6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v3.h @@ -27,6 +27,10 @@ #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 #define QSERDES_V3_COM_PLL_EN 0x044 #define QSERDES_V3_COM_PLL_IVCO 0x048 +#define QSERDES_V3_COM_CMN_IETRIM 0x04c +#define QSERDES_V3_COM_CMN_IPTRIM 0x050 +#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054 +#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 @@ -34,7 +38,10 @@ #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 +#define QSERDES_V3_COM_PLL_CNTRL 0x078 +#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 +#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 @@ -54,10 +61,12 @@ #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 +#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 +#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 @@ -66,21 +75,37 @@ #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 +#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c +#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110 +#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114 +#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 +#define QSERDES_V3_COM_CMN_STATUS 0x124 +#define QSERDES_V3_COM_RESET_SM_STATUS 0x128 +#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c +#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130 +#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134 #define QSERDES_V3_COM_CLK_SELECT 0x138 #define QSERDES_V3_COM_HSCLK_SEL 0x13c +#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140 +#define QSERDES_V3_COM_PLL_ANALOG 0x144 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c +#define QSERDES_V3_COM_SW_RESET 0x150 #define QSERDES_V3_COM_CORE_CLK_EN 0x154 #define QSERDES_V3_COM_C_READY_STATUS 0x158 #define QSERDES_V3_COM_CMN_CONFIG 0x15c +#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 #define QSERDES_V3_COM_DEBUG_BUS0 0x168 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c #define QSERDES_V3_COM_DEBUG_BUS2 0x170 #define QSERDES_V3_COM_DEBUG_BUS3 0x174 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 +#define QSERDES_V3_COM_CMN_MISC1 0x17c +#define QSERDES_V3_COM_CMN_MISC2 0x180 #define QSERDES_V3_COM_CMN_MODE 0x184 +#define QSERDES_V3_COM_CMN_VREG_SEL 0x188 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h index 2c7238df38d7..161e6df30ea8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v3.h @@ -26,6 +26,8 @@ #define QSERDES_V3_TX_TX_POL_INV 0x064 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 #define QSERDES_V3_TX_LANE_MODE_1 0x08c +#define QSERDES_V3_TX_LANE_MODE_2 0x090 +#define QSERDES_V3_TX_LANE_MODE_3 0x094 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 @@ -48,6 +50,7 @@ #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc +#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc -- 2.35.1
