On Fri, Jun 03, 2022 at 11:44:52AM +0300, Dmitry Baryshkov wrote:
> Use newly defined clk_regmap_phy_mux_ops for PCIe pipe clocks to let
> the clock framework automatically park the clock when the clock is
> switched off and restore the parent when the clock is switched on.
>
> Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> drivers/clk/qcom/gcc-sc7280.c | 47 ++++++++++-------------------------
> 1 file changed, 13 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
> index 423627d49719..5a853497d211 100644
> --- a/drivers/clk/qcom/gcc-sc7280.c
> +++ b/drivers/clk/qcom/gcc-sc7280.c
> @@ -17,6 +17,7 @@
> #include "clk-rcg.h"
> #include "clk-regmap-divider.h"
> #include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> #include "common.h"
> #include "gdsc.h"
> #include "reset.h"
> @@ -255,26 +256,6 @@ static const struct clk_parent_data gcc_parent_data_5[] = {
> { .hw = &gcc_gpll0_out_even.clkr.hw },
> };
>
> -static const struct parent_map gcc_parent_map_6[] = {
> - { P_PCIE_0_PIPE_CLK, 0 },
> - { P_BI_TCXO, 2 },
> -};
> -
> -static const struct clk_parent_data gcc_parent_data_6[] = {
> - { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
> - { .fw_name = "bi_tcxo" },
> -};
> -
> -static const struct parent_map gcc_parent_map_7[] = {
> - { P_PCIE_1_PIPE_CLK, 0 },
> - { P_BI_TCXO, 2 },
> -};
> -
> -static const struct clk_parent_data gcc_parent_data_7[] = {
> - { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
> - { .fw_name = "bi_tcxo" },
> -};
> -
> static const struct parent_map gcc_parent_map_8[] = {
> { P_BI_TCXO, 0 },
> { P_GCC_GPLL0_OUT_MAIN, 1 },
> @@ -369,32 +350,30 @@ static const struct clk_parent_data gcc_parent_data_15[] = {
> { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
> };
>
> -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
> .reg = 0x6b054,
> - .shift = 0,
> - .width = 2,
> - .parent_map = gcc_parent_map_6,
> .clkr = {
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_0_pipe_clk_src",
> - .parent_data = gcc_parent_data_6,
> - .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> - .ops = &clk_regmap_mux_closest_ops,
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
No need to initialise fw_name and name on the same line here.
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_phy_mux_ops,
> },
> },
> };
>
> -static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
> +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
> .reg = 0x8d054,
> - .shift = 0,
> - .width = 2,
> - .parent_map = gcc_parent_map_7,
> .clkr = {
> .hw.init = &(struct clk_init_data){
> .name = "gcc_pcie_1_pipe_clk_src",
> - .parent_data = gcc_parent_data_7,
> - .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> - .ops = &clk_regmap_mux_closest_ops,
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
Same here.
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_phy_mux_ops,
> },
> },
> };
Johan
