On 2022-05-27 22:38:24, Dmitry Baryshkov wrote: > [..] > > #define INTF_CFG2_DATABUS_WIDEN BIT(0) > > #define INTF_CFG2_DATA_HCTL_EN BIT(4) > > > > +#define INTF_MISR_CTRL 0x180 > > +#define INTF_MISR_SIGNATURE 0x184 > > +#define INTF_MISR_FRAME_COUNT_MASK 0xFF > > +#define INTF_MISR_CTRL_ENABLE BIT(8) > > +#define INTF_MISR_CTRL_STATUS BIT(9) > > +#define INTF_MISR_CTRL_STATUS_CLEAR BIT(10) > > +#define INTF_MISR_CTRL_FREE_RUN_MASK BIT(31) > > I'm tempted to ask to move these bits to some common header. Is there > any other hardware block which uses the same bitfields to control MISR? Can we use the "rnndb" register XML and bindings generator for DPU, similar to how it is currently used for Adreno/freedreno and the DSI kernel drivers? - Marijn
