On Tue, 24 May 2022 at 00:38, Marijn Suijten
<marijn.suijten@xxxxxxxxxxxxxx> wrote:
>
> parent_hw pointers are easier to manage and cheaper to use than
> repeatedly formatting the parent name and subsequently leaving the clk
> framework to perform lookups based on that name.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 52 +++++++++-------------
> 1 file changed, 22 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> index 48eab80b548e..6926c8ff6255 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
> @@ -519,7 +519,7 @@ static int dsi_28nm_pll_restore_state(struct msm_dsi_phy *phy)
>
> static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **provided_clocks)
> {
> - char clk_name[32], parent1[32], parent2[32], vco_name[32];
> + char clk_name[32], vco_name[32];
While we are at it, we might also get rid of vco_name and use clk_name
everywhere.
> struct clk_init_data vco_init = {
> .parent_data = &(const struct clk_parent_data) {
> .fw_name = "ref", .name = "xo",
> @@ -529,7 +529,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
> .flags = CLK_IGNORE_UNUSED,
> };
> struct device *dev = &pll_28nm->phy->pdev->dev;
> - struct clk_hw *hw;
> + struct clk_hw *hw, *analog_postdiv, *indirect_path_div2, *byte_mux;
> int ret;
>
> DBG("%d", pll_28nm->phy->id);
> @@ -546,48 +546,40 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
> return ret;
>
> snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> - hw = devm_clk_hw_register_divider(dev, clk_name,
> - parent1, CLK_SET_RATE_PARENT,
> + analog_postdiv = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
> + &pll_28nm->clk_hw, CLK_SET_RATE_PARENT,
> pll_28nm->phy->pll_base +
> - REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
> - 0, 4, 0, NULL);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, 0, 4, 0, NULL);
The diff is already hard enough to read. Could you please drop
syntax/whitespace/newline changes?
> + if (IS_ERR(analog_postdiv))
> + return PTR_ERR(analog_postdiv);
>
> snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);
> - snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id);
> - hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> - parent1, CLK_SET_RATE_PARENT,
> - 1, 2);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + indirect_path_div2 = devm_clk_hw_register_fixed_factor_parent_hw(dev,
> + clk_name, analog_postdiv, CLK_SET_RATE_PARENT, 1, 2);
> + if (IS_ERR(indirect_path_div2))
> + return PTR_ERR(indirect_path_div2);
>
> snprintf(clk_name, 32, "dsi%dpll", pll_28nm->phy->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> - hw = devm_clk_hw_register_divider(dev, clk_name,
> - parent1, 0, pll_28nm->phy->pll_base +
> - REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
> - 0, 8, 0, NULL);
> + hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
> + &pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base +
> + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, 0, 8, 0, NULL);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
> provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
>
> snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
> - snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id);
> - snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->phy->id);
> - hw = devm_clk_hw_register_mux(dev, clk_name,
> - ((const char *[]){
> - parent1, parent2
> + byte_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
> + ((const struct clk_hw *[]){
> + &pll_28nm->clk_hw,
> + indirect_path_div2,
> }), 2, CLK_SET_RATE_PARENT, pll_28nm->phy->pll_base +
> REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(byte_mux))
> + return PTR_ERR(byte_mux);
>
> snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->phy->id);
> - snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id);
> - hw = devm_clk_hw_register_fixed_factor(dev, clk_name,
> - parent1, CLK_SET_RATE_PARENT, 1, 4);
> + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
> + byte_mux, CLK_SET_RATE_PARENT, 1, 4);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
> provided_clocks[DSI_BYTE_PLL_CLK] = hw;
> --
> 2.36.1
>
--
With best wishes
Dmitry
