Recent Qualcomm platforms have APCS collapse-vote registers that allow
for sharing GDSCs with other masters (e.g. LPASS).
Add support for using such vote registers instead of the control
register when updating the GDSC power state.
Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
drivers/clk/qcom/gdsc.c | 9 +++++++--
drivers/clk/qcom/gdsc.h | 4 ++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index c676416e685f..6f746158d28f 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -137,8 +137,13 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
u32 reg, mask;
int ret;
- reg = sc->gdscr;
- mask = SW_COLLAPSE_MASK;
+ if (sc->collapse_mask) {
+ reg = sc->collapse_ctrl;
+ mask = sc->collapse_mask;
+ } else {
+ reg = sc->gdscr;
+ mask = SW_COLLAPSE_MASK;
+ }
ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
if (ret)
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index ad313d7210bd..5de48c9439b2 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -18,6 +18,8 @@ struct reset_controller_dev;
* @pd: generic power domain
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
+ * @collapse_ctrl: APCS collapse-vote register
+ * @collapse_mask: APCS collapse-vote mask
* @gds_hw_ctrl: gds_hw_ctrl register
* @cxcs: offsets of branch registers to toggle mem/periph bits in
* @cxc_count: number of @cxcs
@@ -35,6 +37,8 @@ struct gdsc {
struct generic_pm_domain *parent;
struct regmap *regmap;
unsigned int gdscr;
+ unsigned int collapse_ctrl;
+ unsigned int collapse_mask;
unsigned int gds_hw_ctrl;
unsigned int clamp_io_ctrl;
unsigned int *cxcs;
--
2.35.1
