Re: [PATCH v6 3/5] clk: qcom: gcc-sm8450: use new clk_regmap_pipe_src_ops for PCIe pipe clocks

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On 18/05/2022 20:59, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-05-13 10:53:37)
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 593a195467ff..a140a89b73b4 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -239,17 +218,21 @@ static const struct clk_parent_data gcc_parent_data_11[] = {
         { .fw_name = "bi_tcxo" },
  };

-static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
         .reg = 0x7b060,
         .shift = 0,
         .width = 2,
-       .parent_map = gcc_parent_map_4,
+       .phy_src_val = 0, /* pipe_clk */

Make a define? PCIE0_PIPE_CLK_SRC_VAL and drop the comment?

This value can change between the muxes. Thus I'd prefer not to do this.
Compare it with the parent_maps, where we do not use defines for the 'val' part.


+       .ref_src_val = 2, /* bi_tcxo */
         .clkr = {
                 .hw.init = &(struct clk_init_data){
                         .name = "gcc_pcie_0_pipe_clk_src",
-                       .parent_data = gcc_parent_data_4,
-                       .num_parents = ARRAY_SIZE(gcc_parent_data_4),
-                       .ops = &clk_regmap_mux_closest_ops,
+                       .parent_data = &(const struct clk_parent_data){
+                               .fw_name = "pcie_0_pipe_clk",
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_regmap_phy_mux_ops,
                 },
         },
  };


--
With best wishes
Dmitry



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