Re: [PATCH] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs

[Shreyas K K <quic_shrekk@xxxxxxxxxxx>]

Hi Sai,

On 5/11/2022 4:43 PM, Sai Prakash Ranjan wrote:
> Hi Shreyas,
>
> On 5/11/2022 1:32 PM, Shreyas K K wrote:
> > Add KRYO4XX gold/big cores to the list of CPUs that need the
> > repeat TLBI workaround. Apply this to the affected
> > KRYO4XX cores (rcpe to rdpe).
> >
> > The variant and revision bits are implementation defined and are
> > different from the their Cortex CPU counterparts on which they are
> > based on, i.e., (r0p0 to r1p0) is equivalent to (rcpe to rdpe).
> >
> > Signed-off-by: Shreyas K K <quic_shrekk@xxxxxxxxxxx>
> > ---
> >   Documentation/arm64/silicon-errata.rst | 3 +++
> >   arch/arm64/kernel/cpu_errata.c         | 2 ++
> >   2 files changed, 5 insertions(+)
> >
> > diff --git a/Documentation/arm64/silicon-errata.rst 
> > b/Documentation/arm64/silicon-errata.rst
> > index 466cb9e89047..d27db84d585e 100644
> > --- a/Documentation/arm64/silicon-errata.rst
> > +++ b/Documentation/arm64/silicon-errata.rst
> > @@ -189,6 +189,9 @@ stable kernels.
> > +----------------+-----------------+-----------------+-----------------------------+
> >   | Qualcomm Tech. | Kryo4xx Silver  | N/A             | 
> > ARM64_ERRATUM_1024718       |
> > +----------------+-----------------+-----------------+-----------------------------+
> > +| Qualcomm Tech. | Kryo4xx Gold    | N/A             | 
> > ARM64_ERRATUM_1286807       |
> > ++----------------+-----------------+-----------------+-----------------------------+ 
> >
> > +
> > +----------------+-----------------+-----------------+-----------------------------+
> >   | Fujitsu        | A64FX           | E#010001        | 
> > FUJITSU_ERRATUM_010001      |
> > +----------------+-----------------+-----------------+-----------------------------+
> > diff --git a/arch/arm64/kernel/cpu_errata.c 
> > b/arch/arm64/kernel/cpu_errata.c
> > index 4c9b5b4b7a0b..2518657e6de1 100644
> > --- a/arch/arm64/kernel/cpu_errata.c
> > +++ b/arch/arm64/kernel/cpu_errata.c
> > @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities 
> > arm64_repeat_tlbi_list[] = {
> >   #ifdef CONFIG_ARM64_ERRATUM_1286807
> >       {
> >           ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
> > +        /* Kryo4xx Gold (rcpe to rdpe) => (r0p0 to r1p0) */
> > +        ERRATA_MIDR_RANGE(QCOM_CPU_PART_KRYO_4XX_GOLD, 0xc, 0xe, 
> > 0xd, 0xe),
> >       },
> >   #endif
> >       {},
>
> Why not include r2p0 and r3p0 which are affected by this erratum? I 
> see these revisions are present
> in our SoCs as per the document.
>
> Thanks,
> Sai

Acknowledged. Changing in the next version.

Thanks,
Shreyas