From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
Add the CBF PLL register to the kryocc node and assign a frequency
to the clock.
This makes sure the core cluster interconnect is running at a decent
speed, so that it's no longer a pain to use the device with all cores
enabled.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>
Signed-off-by: Yassine Oudjana <yassine.oudjana@xxxxxxxxx>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 205af7b479a8..51ae3cbe75d3 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2698,7 +2698,10 @@ apss_merge_funnel_out: endpoint {
kryocc: clock-controller@6400000 {
compatible = "qcom,msm8996-apcc";
- reg = <0x06400000 0x90000>;
+ reg = <0x06400000 0x90000>, <0x09a11000 0x10000>;
+
+ assigned-clocks = <&kryocc 2>;
+ assigned-clock-rates = <1382400000>;
clock-names = "xo";
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
--
2.36.0
