On Thu, May 05, 2022 at 04:54:05PM +0300, Dmitry Baryshkov wrote: > On some of Qualcomm platforms each group of 32 MSI vectors is routed to the > separate GIC interrupt. Thus to receive higher MSI vectors properly, > add separate msi_host_init()/msi_host_deinit() handling additional host > IRQs. msi_host_init() has 1 user (keystone) as it doesn't use the DWC MSI controller. But QCom does given the access to PCIE_MSI_INTR0_STATUS, so mutiple MSI IRQ outputs must have been added in newer versions of the DWC IP. If so, it's only a matter of time for another platform to do the same thing. Maybe someone from Synopsys could confirm? Therefore this should all be handled in the DWC core. In general, I don't want to see more users nor more ops if we don't have to. Let's not create ops for what can be handled as data. AFAICT, this is just number of MSIs and # of MSIs per IRQ. It seems plausible another platform could do something similar and supporting it in the core code wouldn't negatively impact other platforms. Rob
