Add the reset register offset for clock gating.
Fixes: a3afe2a969cd ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers").
Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
---
[v1]
* This patch has a dependency on the patch under review:
https://lore.kernel.org/lkml/20220503113246.13857-1-quic_tdas@xxxxxxxxxxx/T/#u
https://lore.kernel.org/lkml/20220503164635.23876-1-quic_tdas@xxxxxxxxxxx/T/#t
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 477a754741a1..d5c4ffcf6546 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1985,13 +1985,15 @@
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
- reg = <0 0x03300000 0 0x30000>;
+ reg = <0 0x03300000 0 0x30000>,
+ <0 0x032a9000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
};
lpass_aon: clock-controller@3380000 {
--
2.17.1
