Quoting Dmitry Baryshkov (2022-05-01 12:56:20)
> Remove dividers that are not recommended for DSI DPHY mode when setting
Is "DPHY" intentional or just "PHY" should be here?
> up the clock tree for the DSI pixel clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 6e506feb111f..66ed1919a1db 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
> snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
> snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
> - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
> - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
>
> hw = devm_clk_hw_register_mux(dev, clk_name,
> ((const char *[]){
> - parent, parent2, parent3, parent4
> - }), 4, 0, pll_7nm->phy->base +
> + parent, parent2,
> + }), 2, 0, pll_7nm->phy->base +
> REG_DSI_7nm_PHY_CMN_CLK_CFG1,
> - 0, 2, 0, NULL);
> + 0, 1, 0, NULL);
Can you followup with a patch to move to clk_parent_data instead of
strings?
