On Sat, Apr 30, 2022 at 08:30:08AM -0700, Kaushal Kumar wrote:
> Add devicetree node to enable support for QPIC
> NAND controller on Qualcomm SDX65 platform.
> Since there is no "aon" clock in SDX65, a dummy
> clock is provided.
>
> Signed-off-by: Kaushal Kumar <quic_kaushalk@xxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index d6a6087..a75e9f1 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -37,6 +37,12 @@
> clock-output-names = "sleep_clk";
> #clock-cells = <0>;
> };
> +
> + nand_clk_dummy: nand-clk-dummy {
> + compatible = "fixed-clock";
> + clock-frequency = <32764>;
> + #clock-cells = <0>;
> + };
> };
>
> cpus {
> @@ -211,6 +217,22 @@
> status = "disabled";
> };
>
> + qpic_nand: nand-controller@1b30000 {
> + compatible = "qcom,sdx55-nand";
> + reg = <0x01b30000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&rpmhcc RPMH_QPIC_CLK>,
> + <&nand_clk_dummy>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0x01f40000 0x40000>;
> --
> 2.7.4
>
