On Thu, Apr 28, 2022 at 06:11:44AM -0700, Bjorn Andersson wrote: > On Thu 21 Apr 03:20 PDT 2022, Johan Hovold wrote: > > > Some QMP PHYs need to remux to their pipe clock input to the pipe clock > > output generated by the PHY before powering on the PHY and restore the > > default source during power down. > > > > Add support for an optional pipe clock mux which will be reparented to > > the generated pipe clock before powering on the PHY and restored to the > > default reference source on power off. > > > > After considering this for a while, I have two objections to doing this > explicitly: > > 1) The QMP block is fed &gcc_pcie_N_pipe_clk (and on sc8280xp) > gcc_pcie_N_pipediv2_clk. But neither of these clocks are the mux, so > what this patch (and the existing muxing logic in the controller) does > is to poke into gcc "internals". I agree that this is perhaps the strongest argument against describing the mux in DT (as is also currently done for sc7280). > 2) The actual reason for the mux dance is that toggling the associated > GDSC without a valid parent of this clock would cause the clock to lock > up and GDSC transition to time out. This property is shared with a wide > range of other clocks (so far we have 84 users of clk_rcg2_shared_ops on > sc8280xp). Right, but the situation with rcg2 is a little different. From what I gather the problem there is that some downstream clock could have been enabled by some other part of the system behind the kernel's back and then things go wrong when the kernel configures the clock. Here it is the kernel that controls the source of the pipe clock mux (the PHY PLL) and knows when the source is valid (and the PHY is both provider and consumer of the pipe clock). For rcg2, there's no choice but to work around the hardware in the clock driver, while for QMP the PHY power sequences could be made explicit in the driver: clk_prepare_enable(pipe); clk_set_parent(pipe_src, pll); start_pll(); stop_pll(); clk_set_parent(pipe_src, xo); clk_disable_unprepare(pipe); Note that with the above sequences it would be possible to drop the pipe clock BRANCH_HALT_SKIP flag, which is only there in the clock driver because of the how the PHY works (i.e. that the pipe clock must be ungated before the PLL is started). (This wouldn't be possible with a pipe-mux implementation in the clock driver since the parent mux would be enabled before the child pipe clock.) But sure, the requirement to restore XO to prevent a later GDSC hang has little to do with the PHY. > It would be nice if clk_summary would represent the real state of these > clocks, but unfortunately I don't think the state matches reality with > this approach either. > > E.g. we prepare/enable the pipe clock before setting > QPHY_POWER_DOWN_CONTROL, during this time there's shouldn't be any pipe > clock coming out of the PHY... Right, there's a small window there where the source is still off (due to hardware requirements), but at least the topology is always reported correctly, which is really useful when dealing with boot handover. I have an sc8280xp here where the boot firmware leaves the pipe clock muxed in despite the GDSC being disabled. Fortunately, it doesn't seem to trigger the lockup when toggling the GDSC as it does on an sa8540p. My concerns are otherwise mostly related to the implementation of the safe-mux (e.g. ad-hoc, missing locking) and can probably be addressed. As an example, with the current implementation it is not possible to use an assigned clock parent in DT to make sure that the XO source is selected before toggling the GDSC. The muxing doesn't happen until the pipe clock is enabled, which is much too late in case the boot firmware left the pipe clock muxed in, and when enabling the pipe clock you really want the PHY PLL as source and not the cached XO. Can you still drop the current safe-mux patches from your tree or would they need to be fixed up incrementally? I think you merged v2, but there's already a v3 out (addressing the hardcoded mux configuration values). Johan
