On 23/04/2022 01:44, Stephen Boyd wrote: > Quoting Krzysztof Kozlowski (2022-04-11 08:43:45) >> Devices might need to control several clocks when scaling the frequency >> and voltage. Example is the Universal Flash Storage (UFS) which scales >> several independent clocks with change of performance levels. >> >> Add parsing of multiple clocks and clock names and scale all of them, >> when needed. If only one clock is provided, the code should behave the >> same as before. >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> >> --- > > I vaguely recall that scaling more than one clk with an OPP table is > confusing? I think it's because things like dev_pm_opp_find_freq_ceil() > don't make sense when there's more than one frequency table. How is that > handled here? The assumption (which might need better documentation) is that first clock frequency is the main one: 1. It is still in opp->rate field, so it is used everywhere when OPPs are compared/checked for rates. 1. Usually is used also in opp-table nodes names. The logical explanation is that devices has some main operating frequency, e.g. the core clock, and this determines the performance. In the same time such device might not be able to scale this on core clock independently from others, this this patches. Best regards, Krzysztof
