On Aug 19, 2014, at 5:15 PM, Lina Iyer <lina.iyer@xxxxxxxxxx> wrote:
> Each cpu or an L2$ has an SPM device. They are identical instances of
> the same SPM block. This allows for multiple instances be grouped and
> managed collectively. spm-devices.c is the SPM device manager managing
> multiple SPM devices on top of the driver layer.
>
> Device configuration of each SPM is picked up from the DTS. The hardware
> configuration of each of the SPM is handled by the spm.c driver.
>
> Signed-off-by: Praveen Chidamabram <pchidamb@xxxxxxxxxxxxxx>
> Signed-off-by: Murali Nalajala <mnalajal@xxxxxxxxxxxxxx>
> Signed-off-by: Lina Iyer <lina.iyer@xxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/arm/msm/spm.txt | 47 +++++
> drivers/soc/qcom/Kconfig | 8 +
> drivers/soc/qcom/Makefile | 2 +-
> drivers/soc/qcom/spm-devices.c | 198 ++++++++++++++++++++++
> include/soc/qcom/spm.h | 34 ++++
> 5 files changed, 288 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.txt
> create mode 100644 drivers/soc/qcom/spm-devices.c
> create mode 100644 include/soc/qcom/spm.h
>
> diff --git a/Documentation/devicetree/bindings/arm/msm/spm.txt b/Documentation/devicetree/bindings/arm/msm/spm.txt
> new file mode 100644
> index 0000000..318e024
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/spm.txt
> @@ -0,0 +1,47 @@
> +* Subsystem Power Manager (SAW2)
> +
> +S4 generation of MSMs have SPM hardware blocks to control the Application
> +Processor Sub-System power. These SPM blocks run individual state machine
> +to determine what the core (L2 or Krait/Scorpion) would do when the WFI
> +instruction is executed by the core.
> +
> +The devicetree representation of the SPM block should be:
> +
> +Required properties
> +
> +- compatible: Could be one of -
> + "qcom,spm-v2.1"
> + "qcom,spm-v3.0"
> +- reg: The physical address and the size of the SPM's memory mapped registers
> +- qcom,cpu: phandle for the CPU that the SPM block is attached to.
> + This field is required on only for SPMs that control the CPU.
This should probably moved to optional since not ALL spm nodes would have it.
> +- qcom,saw2-cfg: SAW2 configuration register
> +- qcom,saw2-spm-dly: Provides the values for the SPM delay command in the SPM
> + sequence
> +- qcom,saw2-spm-ctl: The SPM control register
Where is the code that uses "qcom,saw2-spm-dly” & "qcom,saw2-spm-ctl"
> +
> +Optional properties
> +
> +- qcom,saw2-spm-cmd-wfi: The WFI command sequence
> +- qcom,saw2-spm-cmd-ret: The Retention command sequence
> +- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence
> +- qcom,saw2-spm-cmd-pc: The Power Collapse command sequence. This sequence may
> + turn off other SoC components.
> +- qcom,saw2-spm-cmd-gdhs: GDHS (Globally Distributed Head Switch) command
> + sequence. This sequence will retain the memory but turn off the logic.
> +-
> +Example:
> + spm@f9089000 {
> + compatible = "qcom,spm-v2.1";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xf9089000 0x1000>;
> + qcom,cpu = <&CPU0>;
> + qcom,saw2-cfg = <0x1>;
> + qcom,saw2-spm-dly= <0x20000400>;
> + qcom,saw2-spm-ctl = <0x1>;
> + qcom,saw2-spm-cmd-wfi = [03 0b 0f];
> + qcom,saw2-spm-cmd-spc = [00 20 50 80 60 70 10 92
> + a0 b0 03 68 70 3b 92 a0 b0
> + 82 2b 50 10 30 02 22 30 0f];
> + };
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 7dcd554..d467767 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -11,3 +11,11 @@ config QCOM_GSBI
>
> config QCOM_SCM
> bool
> +
> +config QCOM_PM
> + bool "Qualcomm Power Management"
> + depends on PM && ARCH_QCOM && OF
ARCH_QCOM implies OF
> + help
> + QCOM Platform specific power driver to manage cores and L2 low power
> + modes. It interface with various system drivers to put the cores in
> + low power modes.
>
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