On Wed, Apr 13, 2022 at 09:56:46AM -0600, Jeffrey Hugo wrote:
> From: Bhaumik Bhatt <bbhatt@xxxxxxxxxxxxxx>
>
> As of now, MMIO writes done after ready state transition use the
> mhi_write_reg_field() API even though the whole register is being
> written in most cases. Optimize this process by using mhi_write_reg()
> API instead for those writes and use the mhi_write_reg_field()
> API for MHI config registers only.
>
> Signed-off-by: Bhaumik Bhatt <bbhatt@xxxxxxxxxxxxxx>
> Reviewed-by: Hemant Kumar <hemantk@xxxxxxxxxxxxxx>
> Reviewed-by: Jeffrey Hugo <quic_jhugo@xxxxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Signed-off-by: Jeffrey Hugo <quic_jhugo@xxxxxxxxxxx>
> ---
> drivers/bus/mhi/host/init.c | 62 ++++++++++++++++++++++-----------------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
> index 9ac93b7..04c409b 100644
> --- a/drivers/bus/mhi/host/init.c
> +++ b/drivers/bus/mhi/host/init.c
> @@ -425,74 +425,65 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
> struct device *dev = &mhi_cntrl->mhi_dev->dev;
> struct {
> u32 offset;
> - u32 mask;
> u32 val;
> } reg_info[] = {
> {
> - CCABAP_HIGHER, U32_MAX,
> + CCABAP_HIGHER,
> upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
> },
> {
> - CCABAP_LOWER, U32_MAX,
> + CCABAP_LOWER,
> lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
> },
> {
> - ECABAP_HIGHER, U32_MAX,
> + ECABAP_HIGHER,
> upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
> },
> {
> - ECABAP_LOWER, U32_MAX,
> + ECABAP_LOWER,
> lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
> },
> {
> - CRCBAP_HIGHER, U32_MAX,
> + CRCBAP_HIGHER,
> upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
> },
> {
> - CRCBAP_LOWER, U32_MAX,
> + CRCBAP_LOWER,
> lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
> },
> {
> - MHICFG, MHICFG_NER_MASK,
> - mhi_cntrl->total_ev_rings,
> - },
> - {
> - MHICFG, MHICFG_NHWER_MASK,
> - mhi_cntrl->hw_ev_rings,
> - },
> - {
> - MHICTRLBASE_HIGHER, U32_MAX,
> + MHICTRLBASE_HIGHER,
> upper_32_bits(mhi_cntrl->iova_start),
> },
> {
> - MHICTRLBASE_LOWER, U32_MAX,
> + MHICTRLBASE_LOWER,
> lower_32_bits(mhi_cntrl->iova_start),
> },
> {
> - MHIDATABASE_HIGHER, U32_MAX,
> + MHIDATABASE_HIGHER,
> upper_32_bits(mhi_cntrl->iova_start),
> },
> {
> - MHIDATABASE_LOWER, U32_MAX,
> + MHIDATABASE_LOWER,
> lower_32_bits(mhi_cntrl->iova_start),
> },
> {
> - MHICTRLLIMIT_HIGHER, U32_MAX,
> + MHICTRLLIMIT_HIGHER,
> upper_32_bits(mhi_cntrl->iova_stop),
> },
> {
> - MHICTRLLIMIT_LOWER, U32_MAX,
> + MHICTRLLIMIT_LOWER,
> lower_32_bits(mhi_cntrl->iova_stop),
> },
> {
> - MHIDATALIMIT_HIGHER, U32_MAX,
> + MHIDATALIMIT_HIGHER,
> upper_32_bits(mhi_cntrl->iova_stop),
> },
> {
> - MHIDATALIMIT_LOWER, U32_MAX,
> + MHIDATALIMIT_LOWER,
> lower_32_bits(mhi_cntrl->iova_stop),
> },
> - { 0, 0, 0 }
> + {0, 0}
> };
>
> dev_dbg(dev, "Initializing MHI registers\n");
> @@ -533,13 +524,22 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
> mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
>
> /* Write to MMIO registers */
> - for (i = 0; reg_info[i].offset; i++) {
> - ret = mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
> - reg_info[i].mask, reg_info[i].val);
> - if (ret) {
> - dev_err(dev, "Unable to write to MMIO registers");
> - return ret;
> - }
> + for (i = 0; reg_info[i].offset; i++)
> + mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,
> + reg_info[i].val);
> +
> + ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK,
> + mhi_cntrl->total_ev_rings);
> + if (ret) {
> + dev_err(dev, "Unable to read MHICFG register\n");
"Unable to write"?
> + return ret;
> + }
> +
> + ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK,
> + mhi_cntrl->hw_ev_rings);
> + if (ret) {
> + dev_err(dev, "Unable to read MHICFG register\n");
Same here.
Thanks,
Mani
> + return ret;
> }
>
> return 0;
> --
> 2.7.4
>
