On Tue, Apr 12, 2022 at 01:45:37PM -0500, Bjorn Andersson wrote: > On Fri 08 Apr 06:15 CDT 2022, Lorenzo Pieralisi wrote: > > > On Wed, Mar 23, 2022 at 11:50:06AM +0300, Dmitry Baryshkov wrote: > > > On recent Qualcomm platforms the QMP PIPE clocks feed into a set of > > > muxes which must be parked to the "safe" source (bi_tcxo) when > > > corresponding GDSC is turned off and on again. Currently this is > > > handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src > > > clock. However the same code sequence should be applied in the > > > pcie-qcom endpoint, USB3 and UFS drivers. > > > > > > Rather than copying this sequence over and over again, follow the > > > example of clk_rcg2_shared_ops and implement this parking in the > > > enable() and disable() clock operations. As we are changing the parent > > > behind the back of the clock framework, also implement custom > > > set_parent() and get_parent() operations behaving accroding to the clock > > > framework expectations (cache the new parent if the clock is in disabled > > > state, return cached parent). > > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > > > --- > > > drivers/clk/qcom/clk-regmap-mux.c | 78 +++++++++++++++++++++++++++++++ > > > drivers/clk/qcom/clk-regmap-mux.h | 3 ++ > > > 2 files changed, 81 insertions(+) > > > > Need BjornA's ACK on this patch and I can pull the series then. > > > > It seems I have a few more clock patches in the queue which depends on > top of this, so I picked up the three clock branches and pushed a tag > for you to pick up, Lorenzo. I've found a few issues with these clock patches and I'm starting to think we should consider handling the muxing in the PHY driver instead. Dmitry just posted a v2, which I'll comment on: https://lore.kernel.org/all/20220412193839.2545814-1-dmitry.baryshkov@xxxxxxxxxx/ Please take a look at that before merging the clock changes. Johan
