Re: [PATCH v8 1/2] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

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On 4/12/2022 8:03 PM, Bjorn Andersson wrote:
Thanks for your time Bjorn!!!
On Tue 12 Apr 08:14 CDT 2022, Srinivasa Rao Mandadapu wrote:

Add pinmux nodes for primary and secondary I2S for SC7280 based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++
  arch/arm64/boot/dts/qcom/sc7280.dtsi     | 40 ++++++++++++++++++++++++++++++++
  2 files changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index ecbf2b8..1fc94b5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -359,6 +359,20 @@
  	bias-disable;
  };
+&mi2s1_data0 {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&mi2s1_sclk {
+	drive-strength = <6>;
+	bias-disable;
+};
+
+&mi2s1_ws {
+	drive-strength = <6>;
+};
+
  &pm7325_gpios {
  	key_vol_up_default: key-vol-up-default {
  		pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f0b64be..6e6cfeda 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3522,6 +3522,46 @@
  				function = "edp_hot";
  			};
+ mi2s0_data0: mi2s0-data0 {
Are these ever going to be selected individually, or could this be:

mi2s0_state: mi2s0-state {
	data0 {
		...;
	};

	data1 {
		...;
	};

	mclk {
		...;
	};

	etc
};

mi2s1-state {
	...;
};

And then a single pinctrl-0 = <&mi2c0_state>;

Regards,
Bjorn

We are not selecting individually. Actually we were following the same, but Doug Anderson suggested this way of handling in 1st version of patches.

So changed accordingly.


+				pins = "gpio98";
+				function = "mi2s0_data0";
+			};
+
+			mi2s0_data1: mi2s0-data1 {
+				pins = "gpio99";
+				function = "mi2s0_data1";
+			};
+
+			mi2s0_mclk: mi2s0-mclk {
+				pins = "gpio96";
+				function = "pri_mi2s";
+			};
+
+			mi2s0_sclk: mi2s0-sclk {
+				pins = "gpio97";
+				function = "mi2s0_sck";
+			};
+
+			mi2s0_ws: mi2s0-ws {
+				pins = "gpio100";
+				function = "mi2s0_ws";
+			};
+
+			mi2s1_data0: mi2s1-data0 {
+				pins = "gpio107";
+				function = "mi2s1_data0";
+			};
+
+			mi2s1_sclk: mi2s1-sclk {
+				pins = "gpio106";
+				function = "mi2s1_sck";
+			};
+
+			mi2s1_ws: mi2s1-ws {
+				pins = "gpio108";
+				function = "mi2s1_ws";
+			};
+
  			pcie1_clkreq_n: pcie1-clkreq-n {
  				pins = "gpio79";
  				function = "pcie1_clkreqn";
--
2.7.4




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