> + function = "dmic1_clk";
> + };
> +
> + data {
> + pins = "gpio7";
> + function = "dmic1_data";
> + };
> + };
> +
> + dmic01_sleep: dmic01-sleep {
> + clk {
> + pins = "gpio6";
> + function = "dmic1_clk";
> + };
> +
> + data {
> + pins = "gpio7";
> + function = "dmic1_data";
> + };
> + };
> +
> + dmic23: dmic23 {
> + clk {
> + pins = "gpio8";
> + function = "dmic2_clk";
> + };
> +
> + data {
> + pins = "gpio9";
> + function = "dmic2_data";
> + };
> + };
> +
> + dmic23_sleep: dmic23_sleep {
s/dmic23_sleep/dmic23-sleep/ for the node name.
> + clk {
> + pins = "gpio8";
> + function = "dmic2_clk";
> + };
> +
> + data {
> + pins = "gpio9";
> + function = "dmic2_data";
> + };
> + };
> +
> + rx_swr: rx-swr {
> + clk {
> + pins = "gpio3";
> + function = "swr_rx_clk";
> + };
> +
> + data {
> + pins = "gpio4", "gpio5";
> + function = "swr_rx_data";
> + };
> + };
> +
> + rx_swr_sleep: rx-swr-sleep {
> + clk {
> + pins = "gpio3";
> + function = "swr_rx_clk";
> + };
> +
> + data {
> + pins = "gpio4", "gpio5";
> + function = "swr_rx_data";
> + };
> + };
> +
> + tx_swr: tx-swr {
> + clk {
> + pins = "gpio0";
> + function = "swr_tx_clk";
> + };
> +
> + data {
> + pins = "gpio1", "gpio2", "gpio14";
> + function = "swr_tx_data";
> + };
> + };
> +
> + tx_swr_sleep: tx-swr-sleep {
> + clk {
> + pins = "gpio0";
> + function = "swr_tx_clk";
> + };
> +
> + data {
> + pins = "gpio1", "gpio2", "gpio14";
> + function = "swr_tx_data";
> + };
> + };
> + };
> +
> gpu: gpu@3d00000 {
> compatible = "qcom,adreno-635.0", "qcom,adreno";
> reg = <0 0x03d00000 0 0x40000>,
> --
> 2.7.4
>
