On 06-04-22, 02:42, Dmitry Baryshkov wrote:
> On 04/04/2022 19:34, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 98 +++++++++++++++++++++++++++++-
> > 1 file changed, 97 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index eb0be34add45..f3ed6c40b9e1 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -912,6 +912,65 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> > }
> > +static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
> > +{
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, intf_width, reg_ctrl, reg_ctrl2;
> > + u32 slice_per_intf, total_bytes_per_intf;
> > + u32 pkt_per_line;
> > + u32 bytes_in_slice;
> > + u32 eol_byte_num;
> > +
> > + /* first calculate dsc parameters and then program
> > + * compress mode registers
> > + */
> > + intf_width = hdisplay;
> > + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> > +
> > + /* If slice_per_pkt is greater than slice_per_intf
> > + * then default to 1. This can happen during partial
> > + * update.
> > + */
> > + if (slice_per_intf > dsc->drm->slice_count)
> > + dsc->drm->slice_count = 1;
> > +
> > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * dsc->drm->bits_per_pixel, 8);
> > +
> > + dsc->drm->slice_chunk_size = bytes_in_slice;
> > +
> > + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> > +
> > + eol_byte_num = total_bytes_per_intf % 3;
> > + pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> > +
> > + if (is_cmd_mode) /* packet data type */
> > + reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
> > + else
> > + reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
> > +
> > + /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
> > + * registers have similar offsets, so for below common code use
> > + * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
> > + */
> > + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
> > + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
> > + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
> > +
> > + if (is_cmd_mode) {
> > + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> > + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> > +
> > + reg_ctrl |= reg;
> > + reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice);
> > +
> > + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
>
> reg_ctrl, as reported by testing robot
Yes, I did run W=1 check for the patches, with gcc I do not see this
warning :(
I have fixed and will send updated revision shortly
--
~Vinod
