On Wednesday 13 August 2014 01:13 AM, Lina Iyer wrote:
> Add interface layer to abstract and handle hardware specific
> functionality for executing various cpu low power modes in QCOM
> chipsets.
>
> Signed-off-by: Venkat Devarasetty <vdevaras@xxxxxxxxxxxxxx>
> Signed-off-by: Mahesh Sivasubramanian <msivasub@xxxxxxxxxxxxxx>
> Signed-off-by: Lina Iyer <lina.iyer@xxxxxxxxxx>
> ---
> drivers/soc/qcom/Makefile | 2 +-
> drivers/soc/qcom/msm-pm.c | 219 ++++++++++++++++++++++++++++++++++++++++++++++
> include/soc/qcom/pm.h | 39 +++++++++
<snip>
> +{
> + u32 cache_id = 0;
> +
> +#if defined(CONFIG_CPU_V7)
> + u32 sel = 0;
> +
> + asm volatile ("mcr p15, 2, %[ccselr], c0, c0, 0\n\t"
> + "isb\n\t"
> + "mrc p15, 1, %[ccsidr], c0, c0, 0\n\t"
> + :[ccsidr]"=r" (cache_id)
> + :[ccselr]"r" (sel)
Space after ':' is what checkpatch asks. :)
> + );
> + return cache_id & BIT(30);
> +#elif defined(CONFIG_ARM64)
> + u32 sel = 0;
new line missing after declaration.
> + asm volatile("msr csselr_el1, %[ccselr]\n\t"
> + "isb\n\t"
> + "mrs %[ccsidr],ccsidr_el1\n\t"
> + :[ccsidr]"=r" (cache_id)
> + :[ccselr]"r" (sel)
Space after ':' is what checkpatch asks. :)
> + );
> + return cache_id & BIT(30);
> +#else
> +#error No valid CPU arch selected
> +#endif
> +}
> +
>
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