SA8155p ADP board supports the PCIe0 controller in the RC
mode (only). So add the support for the same.
Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Cc: Vinod Koul <vkoul@xxxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 8756c2b25c7e..676e4fe3f848 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -387,6 +387,21 @@ &usb_2_qmpphy {
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l18c_0p88>;
+ vdda-pll-supply = <&vreg_l8c_1p2>;
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l18c_0p88>;
+ vdda-pll-supply = <&vreg_l8c_1p2>;
+};
+
&tlmm {
gpio-reserved-ranges = <0 4>;
--
2.35.1
