On Mon, Feb 28, 2022 at 6:18 AM <michael.srba@xxxxxxxxx> wrote: > > From: Michael Srba <Michael.Srba@xxxxxxxxx> > > Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) > block in the global address space. This bus (and the SSC block itself) is > present on certain qcom SoCs. > > In typical configuration, this bus (as some of the clocks and registers > that we need to manipulate) is not accessible to Linux, and the resources > on this bus are indirectly accessed by communicating with a hexagon CPU > core residing in the SSC block. In this configuration, the hypervisor is > the one performing the bus initialization for the purposes of bringing > the hexagon CPU core out of reset. > > However, it is possible to change the configuration, in which case this > driver will initialize the bus. > > In combination with drivers for resources on the SSC bus, this driver can > aid in debugging, and for example with a TLMM driver can be used to > directly access SSC-dedicated GPIO pins, removing the need to commit > to a particular usecase during hw design. > > Finally, until open firmware for the hexagon core is available, this > approach allows for using sensors hooked up to SSC-dedicated GPIO pins > on mainline Linux simply by utilizing the existing in-tree drivers for > these sensors. > > Signed-off-by: Michael Srba <Michael.Srba@xxxxxxxxx> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@xxxxxxxxx>
