On Thu, 3 Mar 2022 at 11:49, Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx> wrote:
>
> From: Vinod Koul <vkoul@xxxxxxxxxx>
>
> SM8150 SoC supports ethqos ethernet controller so add the node for it
Is it available e.g. in the sm8150 SoC that I have in the phone?
>
> Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
> Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
> [bhsharma: Correct ethernet interrupt numbers and add power-domain]
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 6012322a5984..2ed231767535 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -915,6 +915,33 @@ gpi_dma0: dma-controller@800000 {
> status = "disabled";
> };
>
> + ethernet: ethernet@20000 {
> + compatible = "qcom,sm8150-ethqos";
> + reg = <0x0 0x00020000 0x0 0x10000>,
> + <0x0 0x00036000 0x0 0x100>;
> + reg-names = "stmmaceth", "rgmii";
> + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
> + clocks = <&gcc GCC_EMAC_AXI_CLK>,
> + <&gcc GCC_EMAC_SLV_AHB_CLK>,
> + <&gcc GCC_EMAC_PTP_CLK>,
> + <&gcc GCC_EMAC_RGMII_CLK>;
> + interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_lpi";
> +
> + power-domains = <&gcc EMAC_GDSC>;
> + resets = <&gcc GCC_EMAC_BCR>;
> +
> + iommus = <&apps_smmu 0x3C0 0x0>;
> +
> + snps,tso;
> + rx-fifo-depth = <4096>;
> + tx-fifo-depth = <4096>;
> +
> + status = "disabled";
> + };
> +
> +
> qupv3_id_0: geniqup@8c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x008c0000 0x0 0x6000>;
> --
> 2.35.1
>
--
With best wishes
Dmitry
