On Thu 24 Feb 07:55 PST 2022, Ansuel Smith wrote:
> On Wed, Feb 23, 2022 at 09:55:16PM -0600, Bjorn Andersson wrote:
> > On Thu 17 Feb 17:56 CST 2022, Ansuel Smith wrote:
> >
> > > Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
> > > clocked to 800MHz. Add these missing freq to the gcc driver.
> > >
> >
> > Do we somehow need to ensure that these new frequencies are only
> > available on 8065?
> >
> > Regards,
> > Bjorn
> >
>
> In theory ipq8064 can run the nss cores to this freq. Do you have any
> suggestion on how to limit these 2 clock to the different compatible?
>
What's done in other clock drivers is that we have different
compatibles and then rewrite the clock definitions at probe before
registering the clocks.
It sounds like it's the right thing to do here as well, to avoid the
8064 nss to be overclocked.
Regards,
Bjorn
> > > Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
> > > ---
> > > drivers/clk/qcom/gcc-ipq806x.c | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
> > > index a4bf78fe8678..53a61860063d 100644
> > > --- a/drivers/clk/qcom/gcc-ipq806x.c
> > > +++ b/drivers/clk/qcom/gcc-ipq806x.c
> > > @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
> > >
> > > static struct pll_freq_tbl pll18_freq_tbl[] = {
> > > NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
> > > + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
> > > NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
> > > + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
> > > };
> > >
> > > static struct clk_pll pll18 = {
> > > @@ -2702,7 +2704,9 @@ static const struct freq_tbl clk_tbl_nss[] = {
> > > { 110000000, P_PLL18, 1, 1, 5 },
> > > { 275000000, P_PLL18, 2, 0, 0 },
> > > { 550000000, P_PLL18, 1, 0, 0 },
> > > + { 600000000, P_PLL18, 1, 0, 0 },
> > > { 733000000, P_PLL18, 1, 0, 0 },
> > > + { 800000000, P_PLL18, 1, 0, 0 },
> > > { }
> > > };
> > >
> > > --
> > > 2.34.1
> > >
>
> --
> Ansuel
