There are two different PCIe controllers and PHYs on SM8450, one having one lane and another with two lanes. Add support for both PCIe controllers Changes since v5: - Rebase on 5.17-rc1 - Drop external dependencies. The pipe_clk rework takes too much time to be reviewed. SM8450 works with the current pipe_clk multiplexing code. Fixing pipe_clk will be handled separately. - Drop interconnect support. It will be handled separately for all generations requiring interconnect usage. Changes since v4: - Add PCIe1 support - Change binding accordingly, to use qcom,pcie-sm8450-pcie0 and qcom,pcie-sm8450-pcie1 compatibility strings - Rebase on top of (pending) pipe_clock cleanup/rework patchset Changes since v3: - Fix pcie gpios to follow defined schema as noted by Rob - Fix commit message according to Bjorn's suggestions Changes since v2: - Remove unnecessary comment in struct qcom_pcie_cfg Changes since v1: - Fix capitalization/wording of PCI patch subjects - Add missing gen3x1 specification to PHY table names Dmitry Baryshkov (4): dt-bindings: pci: qcom: Document PCIe bindings for SM8450 PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg PCI: qcom: Add ddrss_sf_tbu flag PCI: qcom: Add SM8450 PCIe support .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++- drivers/pci/controller/dwc/pcie-qcom.c | 93 ++++++++++++------- 2 files changed, 83 insertions(+), 32 deletions(-) -- 2.34.1
