On Thu, Feb 10, 2022 at 08:20:03PM +0530, Manivannan Sadhasivam wrote: > The Qualcomm PCI bridge device (0x0110) found in chipsets such as SM8450 > does not set the command completed bit unless writes to the Slot Command > register change "Control" bits. > > This results in timeouts like below: > > pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) > > Hence, add the device to the command completed quirk to mark commands > "completed" immediately unless they change the "Control" bits. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Applied to pci/hotplug for v5.18, thanks! Should we assume that this erratum will be fixed in future Qualcomm devices? Or should we apply the quirk for all Qualcomm hotplug bridges, as we do for Intel? > --- > drivers/pci/hotplug/pciehp_hpc.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c > index 1c1ebf3dad43..4e4ccf3afbe3 100644 > --- a/drivers/pci/hotplug/pciehp_hpc.c > +++ b/drivers/pci/hotplug/pciehp_hpc.c > @@ -1084,6 +1084,8 @@ static void quirk_cmd_compl(struct pci_dev *pdev) > } > DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, > PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); > +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110, > + PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); > DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400, > PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); > DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, > -- > 2.25.1 >
