Many devices are based on the v2.0 of the ipq8064 SoC. Main difference
is a change in the pci compatible and different way to configre the usb
phy.
Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
---
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++++++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
new file mode 100644
index 000000000000..c082c3cd1a19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&CPU_SPC {
+ status = "okay";
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
--
2.33.1
