On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
> Add LMh nodes for cpu cluster0 and cpu cluster1 for sm8150 SoC.
>
> Signed-off-by: Thara Gopinath <thara.gopinath@xxxxxxxxxx>
Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Daniel, will you please apply patch 1 and 3 through your tree and I can
take this through the qcom dts tree.
Thanks,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 81b4ff2cc4cd..e755d7ab78dd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3650,6 +3650,30 @@ cpufreq_hw: cpufreq@18323000 {
> #freq-domain-cells = <1>;
> };
>
> + lmh_cluster1: lmh@18350800 {
> + compatible = "qcom,sm8150-lmh";
> + reg = <0 0x18350800 0 0x400>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&CPU4>;
> + qcom,lmh-temp-arm-millicelsius = <60000>;
> + qcom,lmh-temp-low-millicelsius = <84500>;
> + qcom,lmh-temp-high-millicelsius = <85000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + lmh_cluster0: lmh@18358800 {
> + compatible = "qcom,sm8150-lmh";
> + reg = <0 0x18358800 0 0x400>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&CPU0>;
> + qcom,lmh-temp-arm-millicelsius = <60000>;
> + qcom,lmh-temp-low-millicelsius = <84500>;
> + qcom,lmh-temp-high-millicelsius = <85000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> wifi: wifi@18800000 {
> compatible = "qcom,wcn3990-wifi";
> reg = <0 0x18800000 0 0x800000>;
> --
> 2.25.1
>
