On Thu, 30 Dec 2021 at 12:25, Rajeev Nandan <quic_rajeevny@xxxxxxxxxxx> wrote: > > Add 10nm dsi phy tuning properties for phy drive strength and > phy drive level adjustemnt. > > Signed-off-by: Rajeev Nandan <quic_rajeevny@xxxxxxxxxxx> > --- > .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > index 4399715..9406982 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml > @@ -35,6 +35,18 @@ properties: > Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and > connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target > > + phy-drive-strength-cfg: > + type: array > + description: > + Register values of DSIPHY_RESCODE_OFFSET_TOP and DSIPHY_RESCODE_OFFSET_BOT > + for all five lanes to adjust the phy drive strength. > + > + phy-drive-level-cfg: > + type: array > + description: > + Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to adjust > + phy drive level/amplitude. Description is incorrect, it's not the RESCODE_OFFSET_TOP register. > + > required: > - compatible > - reg > @@ -64,5 +76,12 @@ examples: > clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > <&rpmhcc RPMH_CXO_CLK>; > clock-names = "iface", "ref"; > + > + phy-drive-strength-cfg = [00 00 > + 00 00 > + 00 00 > + 00 00 > + 00 00]; > + phy-drive-level-cfg = [59 59 59 59 59]; You are writing this value into the PHY_CMN_VREG_CTRL register. So specifying 5 values here does not make sense. > }; > ... > -- > 2.7.4 > -- With best wishes Dmitry
