Re: [PATCH v4 16/16] clk: qcom: gcc-msm8996: start getting rid of xo clk

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On 2021-12-28 07:54:15, Dmitry Baryshkov wrote:
> The "xo" fixed_factor clock is a leftover/hack from a time when we
> couldn't make rpmhcc the root of all clocks. It is going to be removed
> once all users of this clock are converted to use clocks specified
> through the DTS. Replace internal usage of the xo clock with the cxo
> (RPM_SMD_BB_CLK1) parent, specifying xo_board as a fallback.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>

>From https://lore.kernel.org/linux-arm-msm/20211215201153.orgyt6mlmxryrdpn@xxxxxxxxxxxxxx/:

Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>

> ---
>  drivers/clk/qcom/gcc-msm8996.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index 6b36024583b4..e16163706735 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -54,8 +54,8 @@ static struct clk_alpha_pll gpll0_early = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll0_early",
> -			.parent_hws = (const struct clk_hw*[]){
> -				&xo.hw,
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "cxo", .name = "xo_board",
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_ops,
> @@ -131,8 +131,8 @@ static struct clk_alpha_pll gpll4_early = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll4_early",
> -			.parent_hws = (const struct clk_hw*[]){
> -				&xo.hw,
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "cxo", .name = "xo_board",
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_ops,
> @@ -167,7 +167,7 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw }
>  };
>  
> @@ -177,7 +177,7 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_sleep_clk[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
>  };
>  
> @@ -188,7 +188,7 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw },
>  	{ .hw = &gpll0_early_div.hw }
>  };
> @@ -200,7 +200,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw },
>  	{ .hw = &gpll4.clkr.hw }
>  };
> @@ -212,7 +212,7 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw },
>  	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
>  };
> @@ -225,7 +225,7 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw },
>  	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
>  	{ .hw = &gpll0_early_div.hw }
> @@ -239,7 +239,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
>  };
>  
>  static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> -	{ .hw = &xo.hw },
> +	{ .fw_name = "cxo", .name = "xo_board" },
>  	{ .hw = &gpll0.clkr.hw },
>  	{ .hw = &gpll4.clkr.hw },
>  	{ .hw = &gpll0_early_div.hw }
> -- 
> 2.34.1
> 



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