On Wed, Dec 15, 2021 at 06:09:39PM +0100, Loic Poulain wrote: > Add device tree bindings for display clock controller on QCM2290 SoCs. > > Signed-off-by: Loic Poulain <loic.poulain@xxxxxxxxxx> > Reviewed-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > --- > v2: no change > v3: Include dt-bindings header (qcom,dispcc-qcm2290.h) in that commit > > .../bindings/clock/qcom,qcm2290-dispcc.yaml | 87 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,dispcc-qcm2290.h | 34 +++++++++ > 2 files changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > create mode 100644 include/dt-bindings/clock/qcom,dispcc-qcm2290.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > new file mode 100644 > index 00000000..44d5ce7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only dual license > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display Clock & Reset Controller Binding for qcm2290 > + > +maintainers: > + - Loic Poulain <loic.poulain@xxxxxxxxxx> > + > +description: | > + Qualcomm display clock control module which supports the clocks, resets and > + power domains on qcm2290. > + > + See also dt-bindings/clock/qcom,dispcc-qcm2290.h. > + > +properties: > + compatible: > + const: qcom,qcm2290-dispcc > + > + clocks: > + items: > + - description: Board XO source > + - description: Board active-only XO source > + - description: GPLL0 source from GCC > + - description: GPLL0 div source from GCC > + - description: Byte clock from DSI PHY > + - description: Pixel clock from DSI PHY > + > + clock-names: > + items: > + - const: bi_tcxo > + - const: bi_tcxo_ao > + - const: gcc_disp_gpll0_clk_src > + - const: gcc_disp_gpll0_div_clk_src > + - const: dsi0_phy_pll_out_byteclk > + - const: dsi0_phy_pll_out_dsiclk > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> > + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> > + #include <dt-bindings/clock/qcom,rpmcc.h> > + clock-controller@5f00000 { > + compatible = "qcom,qcm2290-dispcc"; > + reg = <0x5f00000 0x20000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_CLK_SRC>, > + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, > + <&dsi0_phy 0>, > + <&dsi0_phy 1>; > + clock-names = "bi_tcxo", > + "bi_tcxo_ao", > + "gcc_disp_gpll0_clk_src", > + "gcc_disp_gpll0_div_clk_src", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,dispcc-qcm2290.h b/include/dt-bindings/clock/qcom,dispcc-qcm2290.h > new file mode 100644 > index 00000000..5b20fb0 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,dispcc-qcm2290.h > @@ -0,0 +1,34 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ dual license > +/* > + * Copyright (c) 2019, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H > +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCM2290_H > + > +/* DISP_CC clocks */ > +#define DISP_CC_PLL0 0 > +#define DISP_CC_MDSS_AHB_CLK 1 > +#define DISP_CC_MDSS_AHB_CLK_SRC 2 > +#define DISP_CC_MDSS_BYTE0_CLK 3 > +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 > +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 > +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 > +#define DISP_CC_MDSS_ESC0_CLK 7 > +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 > +#define DISP_CC_MDSS_MDP_CLK 9 > +#define DISP_CC_MDSS_MDP_CLK_SRC 10 > +#define DISP_CC_MDSS_MDP_LUT_CLK 11 > +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 > +#define DISP_CC_MDSS_PCLK0_CLK 13 > +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 > +#define DISP_CC_MDSS_VSYNC_CLK 15 > +#define DISP_CC_MDSS_VSYNC_CLK_SRC 16 > +#define DISP_CC_SLEEP_CLK 17 > +#define DISP_CC_SLEEP_CLK_SRC 18 > +#define DISP_CC_XO_CLK 19 > +#define DISP_CC_XO_CLK_SRC 20 > + > +#define MDSS_GDSC 0 > + > +#endif > -- > 2.7.4 > >
