On 15/12/2021 12:23, Marijn Suijten wrote:
On 2021-12-15 03:54:15, Dmitry Baryshkov wrote:
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxx>
As with the other SoC patches in this series, you should move:
[PATCH v2 09/15] clk: qcom: camcc-sdm845: use ARRAY_SIZE instead of specifying num_parents
Before this patch (07/15). Otherwise num_parents for all the clocks
using parent_map/names_0 will have to temporarily be changed from 6 down
to 5 to make this bisectable.
Oops, missed this.
- Marijn
---
drivers/clk/qcom/camcc-sdm845.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 1b2cefef7431..545c288a7f98 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -23,7 +23,6 @@ enum {
P_CAM_CC_PLL1_OUT_EVEN,
P_CAM_CC_PLL2_OUT_EVEN,
P_CAM_CC_PLL3_OUT_EVEN,
- P_CORE_BI_PLL_TEST_SE,
};
static const struct parent_map cam_cc_parent_map_0[] = {
@@ -32,7 +31,6 @@ static const struct parent_map cam_cc_parent_map_0[] = {
{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const cam_cc_parent_names_0[] = {
@@ -41,7 +39,6 @@ static const char * const cam_cc_parent_names_0[] = {
"cam_cc_pll1_out_even",
"cam_cc_pll3_out_even",
"cam_cc_pll0_out_even",
- "core_bi_pll_test_se",
};
static struct clk_alpha_pll cam_cc_pll0 = {
--
2.33.0
--
With best wishes
Dmitry
