On Wed, Jul 24, 2013 at 11:37:28AM -0700, Stephen Boyd wrote:
UARTDM serial devices require us to wait for the entire TX fifo to drain before we can change the contents of the NCF_TX register. Furthermore, if we write any characters to the TX fifo within the same clock cycle of changing the NCF_TX register the NCF_TX register won't latch properly. To fix these issues we should read back the NCF_TX register to delay any TX fifo accesses by a clock cycle and we should wait for the TX fifo to drain (instead of just waiting for the fifo to be ready to receive more characters). Failure to do so leads to random NUL bytes interspersed in the output. Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> --- drivers/tty/serial/msm_serial.c | 14 +++++++++----- drivers/tty/serial/msm_serial.h | 1 + 2 files changed, 10 insertions(+), 5 deletions(-)
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