Le 04/10/2024 à 15:21, Arnd Bergmann a écrit :
On Thu, Oct 3, 2024, at 15:29, Vincenzo Frascino wrote:
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a6c69a706fd7..352ef5e1c615 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -308,7 +308,7 @@ static void gen6_check_faults(struct intel_gt *gt)
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
gt_dbg(gt, "Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
+ "\tAddr: 0x%08x\n"
"\tAddress space: %s\n"
"\tSource ID: %d\n"
"\tType: %d\n",
Isn't the type of PAGE_MASK still architecture dependent?
Indeed when I commented that PAGE_MASK was type agnostic I was thinking
about the powerpc PAGE_MASK:
#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
It should probably be possible to generalise it to all architectures.
But if you keep some PAGE_MASK with forced UL type just like:
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
Then that version of PAGE_MASK isn't agnostic and ANDing an int with
that mask makes a long result.
I think you need a cast to either 'int' or 'long' here to
make the corresponding format string work across all
architectures. With the current version of your patch 2/2,
it looks like it has to be %x for architectures with
64-bit phys_addr_t, but %lx for the other ones.
Changing the 'u32 fault' variable to 'unsigned long'
would also work here.
Arnd
