On Sat, May 11, 2024 at 08:49:08PM +0200, John Paul Adrian Glaubitz wrote: > Hi Paul, > > On Fri, 2024-05-10 at 15:28 -0700, Paul E. McKenney wrote: > > > I'm still against dropping pre-EV56 so quickly without a proper phaseout period. > > > Why not wait for the next LTS release? AFAIK pre-EV56 support is not broken, is > > > it? > > > > Sadly, yes, it is, and it has been broken in mainline for almost two > > years. > > Could you elaborate what exactly is broken? I'm just trying to understand the reasoning. First, let's make sure that I completely and correctly understand the situation. The pre-EV56 Alphas have no byte store instruction, correct? If that is in fact correct, what code is generated for a volatile store to a single byte for those CPUs? For example, for this example? char c; ... WRITE_ONCE(c, 3); The rumor I heard is that the compilers will generate a non-atomic read-modify-write instruction sequence in this case, first reading the 32-bit word containing that byte into a register, then substituting the value to be stored into corresponding byte of that register, and finally doing a 32-bit store from that register. Is that the case, or am I confused? Thanx, Paul PS: Or, if you prefer, this example is equivalent: volatile char c; ... c = 3;
