On Mon, Jan 29, 2024 at 07:05:08PM +0100, Ard Biesheuvel wrote:
> From: Ard Biesheuvel <ardb@xxxxxxxxxx>
>
> When executing in long mode, the CR4.PAE and CR4.LA57 control bits
> cannot be updated,
"Long mode requires PAE to be enabled in order to use the 64-bit
page-translation data structures to translate 64-bit virtual addresses
to 52-bit physical addresses."
which is actually already enabled at that point:
cr4 0x20 [ PAE ]
"5-Level paging is enabled by setting CR4[LA57]=1 when EFER[LMA]=1.
CR4[LA57] is ignored when long mode is not active (EFER[LMA]=0)."
and if I had a 5-level guest, it would have LA57 already set too.
So I think you mean "When paging is enabled" as dhansen correctly points
out.
> and so they can simply be preserved rather than reason about whether
> or not they need to be set. CR4.PSE has no effect in long mode so it
> can be omitted.
f4c5ca985012 ("x86_64: Show CR4.PSE on auxiliaries like on BSP")
Please don't forget about git history before doing changes here.
> CR4.PGE is used to flush the TLBs, by clearing it if it was set, and
... to flush TLB entries with the global bit set.
And just like the above commit says, I think the CR4 settings across all
CPUs on the machine should be the same. So we want to keep PSE.
Removing the CONFIG_X86_5LEVEL ifdeffery is nice, OTOH.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
