Hi Yunhui,
On Mon, Jan 29, 2024 at 4:07 AM yunhui cui <cuiyunhui@xxxxxxxxxxxxx> wrote:
>
> Hi Alexandre,
>
> On Sun, Jan 28, 2024 at 8:04 PM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote:
> >
> > The riscv privileged specification mandates to flush the TLB whenever a
> > page directory is modified, so add that to tlb_flush().
> >
> > Fixes: c5e9b2c2ae82 ("riscv: Improve tlb_flush()")
> > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> > ---
> > arch/riscv/include/asm/tlb.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h
> > index 1eb5682b2af6..50b63b5c15bd 100644
> > --- a/arch/riscv/include/asm/tlb.h
> > +++ b/arch/riscv/include/asm/tlb.h
> > @@ -16,7 +16,7 @@ static void tlb_flush(struct mmu_gather *tlb);
> > static inline void tlb_flush(struct mmu_gather *tlb)
> > {
> > #ifdef CONFIG_MMU
> > - if (tlb->fullmm || tlb->need_flush_all)
> > + if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables)
> > flush_tlb_mm(tlb->mm);
>
> Why is it necessary to flush all TLB entries of the process?
That's quite heavy but that's the only to flush any "intermediate"
cache that would cache non-leaf PTEs, the specification mentions this:
"If software modifies a non-leaf PTE, it should execute SFENCE.VMA
with rs1=x0. If any PTE along the traversal path had its G bit set,
rs2 must be x0; otherwise, rs2 should be set to the ASID for which the
translation is being modified."
That was the behaviour before commit c5e9b2c2ae82 ("riscv: Improve
tlb_flush()").
>
> Thanks,
> Yunhui
