On Tue, Jan 9, 2024, at 15:45, Yangyu Chen wrote:
> For some ISAs like RISC-V, which may not support bus broadcast-based
> icache flushing instructions, it's necessary to send IPIs to all of the
> CPUs in the system to flush the icache. This process can be expensive for
> these ISAs and introduce disturbances during performance profiling.
> Limiting the icache flush to occur only when the vma->vm_flags has VM_EXEC
> can help minimize the frequency of these operations.
>
> Signed-off-by: Yangyu Chen <cyy@xxxxxxxxxxxx>
> ---
> include/asm-generic/cacheflush.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/asm-generic/cacheflush.h
> b/include/asm-generic/cacheflush.h
> index 84ec53ccc450..729d51536575 100644
> --- a/include/asm-generic/cacheflush.h
> +++ b/include/asm-generic/cacheflush.h
> @@ -102,7 +102,8 @@ static inline void flush_cache_vunmap(unsigned long
> start, unsigned long end)
> do { \
> instrument_copy_to_user((void __user *)dst, src, len); \
> memcpy(dst, src, len); \
> - flush_icache_user_page(vma, page, vaddr, len); \
> + if (vma->vm_flags & VM_EXEC) \
> + flush_icache_user_page(vma, page, vaddr, len); \
> } while (0)
> #endif
This is not my normal area of expertise, but I wonder if you can't
just do this the same way as alpha and openrisc by having the
condition in architecture specific code.
Arnd
